Component with ultra-high frequency connections in a substrate

ABSTRACT

The present invention relates to contacting technology for signal connections in the substrate of an extremely high frequency module, in particular a microwave or millimeter wave module. The extremely high frequency module contains a) a multilayer substrate having at least two dielectric layers and metallization layers and inter-layer connections, and b) chips positioned on the top of the multilayer substrate. The chips are electrically connected to each other and to the structures in the metallization layers by means of HF connections. The HF connection is realized by means of at least two conductor lines, which exhibit fanning. The present invention allows for simple contacting of chips having small intervals between the external contacts on the multilayer substrate.

The present invention relates to contacting technology for signalconnections in the substrate of an extremely high frequency module, forexample a microwave or millimeter wave module, and a contactingtechnology for such components.

The frequency range between 1 GHz and 30 GHz is called the microwaverange (MW range). The frequency range from 30 GHz upward is called themillimeter wave range (mmw range). Extremely high frequency modulesdiffer from high frequency modules in particular in the fact that forextremely high frequency circuits at 5 GHz and higher as a rule“waveguides,” e.g., microstrip lines and coplanar lines, are used.

Extremely high frequency modules are electronic components which fulfilla variety of functionalities for applications intended for use in thefrequency range from 1 to 100 GHz. Such components may be employed ingeneral in data transmission systems, e.g., for satellite televisionreception, for wireless local data networks—LANs (local area networks),WLANs (wireless LANs), Bluetooth, optical modules such as multiplexers,modulators and transceiver units—as well as for radar and for front-endmodules for broadband communication, e.g., LMDS (local multimediadistribution systems) and directional radio equipment for base stations.

Most modules that operate in the millimeter wave range are producedtoday on the basis of thin film substrates containing integratedcircuits. The thin film substrate can carry one or more chip componentsat the same time. The chip components are attached to the carriersubstrate by means of wire bonding or the flip-chip technique and areconnected to it electronically. The contact paths between the chipcomponents and the substrate are kept as short as possible, so that thesignal losses, which come to light in particular when a componentcontaining open signal-carrying lines is encapsulated with a castingcompound, may be minimized.

Because of relatively high costs, the chip area of the semiconductorchip components is kept very small, which results in correspondinglysmall dimensions of the external contacts of such components. Thecontact size of a microwave IC is usually around 50 to 100 μm; theinterval between the external contacts varies between 100 and 250 μm.For technological reasons, the minimum spacing between two inter-layerconnections in the substrate for example is 225 μm. In principle it ispossible to bring the interval of the external contacts of a microwaveIC to the minimum interval between the inter-layer connections. Thisinvolves an unwanted enlargement of the chip area, however. Anotherproblem is that for technological reasons it is not possible to applyconductor lines of any desired fineness in the substrate or on the topsurface of the substrate.

The object of the present invention is to improve the contactingtechnique between modular components in a microwave or millimeter wavemodule, in order to enable contacting of the semiconductor chipcomponents, which have small intervals between their external contacts,with the metal structures in the module substrate, while maintaining therequisite minimum interval between the inter-layer connections in themodule substrate.

This problem is solved according to the invention by a component havingthe characteristics of claim 1. Advantageous forms of the invention areevident from additional claims.

The invention specifies a component having contacting, which includes amultilayer substrate and at least one chip positioned on the top of themultilayer substrate, having at least two external contacts on thebottom which are electrically connected to the multilayer substrate. Themultilayer substrate has at least two dielectric layers, one positioneddirectly above the other, there being metallization layers provided ontop of, beneath and between the dielectric layers. In each dielectriclayer at least two inter-layer connections (DK1, DK2) are provided toconnect two different metallization layers. The minimum interval bbetween the inter-layer connections in the topmost dielectric layer isselected to be less than or equal to (b≦c) the minimum interval cbetween the inter-layer connections in the deeper layers.

The interval a between at least two of the named external contacts issmaller than the minimum interval b or c between the inter-layerconnections in the dielectric layers.

On the surface of the component is a protective layer, which lies on topof the chip and is designed to protect the chip against environmentalinfluences. Another task of the protective layer is to prevent theliquid casting compound of another covering that needs to be appliedlater from running under the chip and touching the active IC circuitry,which would result in malfunctions, in particular detuning or failure ofthe chip.

The component according to the present invention has at least one highfrequency or extremely high frequency connection (HF connection) betweenelectric conductor lines, selected from the external contacts of the atleast one chip and/or structure of the named metallization layers, whichis provided in a metallization layer of the multilayer substrate. Thehigh frequency or extremely high frequency connection includes at leasttwo conductor lines which are not electrically connected with eachother, and is positioned in one or more metallization layers in themultilayer substrate. The high frequency or extremely high frequencyconnection exhibits fanning of the conductor lines in at least onemetallization layer. It is possible either for at least a part of the HFconnections and DC connections to be positioned on the top or bottom ofthe substrate, or for all the signal lines to be hidden in thesubstrate. The fanning of the conductor lines according to the inventionmay be provided in the topmost metallization layer below the chip area,or else between the dielectric layers.

The HF connection may for example connect at least two external contactsof the same chip. Furthermore, it is also possible for the HF connectionto connect at least one external contact of the chip and at least oneexternal contact of another chip that is positioned on top of themultilayer substrate. It is also possible for the HF connection toconnect at least one metal structure which is positioned in one of themetallization layers in the multilayer substrate with at least oneexternal contact of the chip, or with another metal structure that ispositioned in one of the metallization layers in the multilayersubstrate.

If the interval between at least two external contacts of the chip isequal to or greater than the requisite minimum interval b, the namedexternal contacts preferably lie directly above inter-layer connectionslocated in the topmost dielectric layer.

A chip may contain active or passive components. A chip may also be anencased component.

The chip may be a microwave chip, a millimeter wave chip or an ICcomponent (IC=integrated circuit). The IC component may be in particulara MMIC component (MMIC monolithic microwave integrated circuit).

The active chip components may be constructed for example on the basisof Si, SiGe, GaAs or InP.

Furthermore, the component according to the invention may contain adiscrete component, selected from a capacitor, a coil, a resistor or achip component, which contains at least a part of the followingcircuitry: an RLC circuit, a filter, a switch, a directional coupler, abias network, an antenna, an impedance converter or a matching network.

The chip has one side with metal structures. These metal structuresrepresent in particular at least two external contacts for electricalconnection with the metal structures hidden in the substrate.

The chip is preferably mechanically and electrically connected with thesubstrate and the integrated circuit elements by means of the flip-chiptechnique, with the structured (and possibly surface-sensitive) side ofthe chip facing the top side of the substrate.

In addition to the chip there may be one or more support substrateshaving passive HF structures such as filters or mixers, in particularsupport substrates structured using thin film technology, positioned onthe top of the substrate.

The term substrate is used here to mean all types of planar circuitcarriers. These include ceramic substrates (thin film ceramics, thickfilm ceramics, LTCC=low-temperature cofired ceramics,HTCC=high-temperature cofired ceramics; LTCCs and HTCCs are ceramicmultilayer circuits), polymer substrates (conventional circuit boardssuch as FR4, so-called soft substrates whose polymer base consists forexample of PTFE≈Teflon or polyolefins and which are typically reinforcedwith fiberglass or filled with ceramic powder), or silicon.

In preferred embodiments of the invention the substrate containsintegrated circuit elements. The term circuit element means inparticular an inductance, a capacitance, a connecting line or a delayline, which together may realize for example a resonator, a filtercircuit or a directional coupler. These may be arranged in a knownmanner as conductor lines between, in and on the dielectric layers of asubstrate having multilayer construction, and thus form integratedcircuit elements. Vertical connections between the conductor lines invarious layers (inter-layer connections) are also counted as integratedcircuit elements, since on the one hand they serve to conduct signalsvertically, and on the other hand, in particular at extremely highfrequencies, they constitute both a (parasitic) inductance and a(parasitic) capacitance. A plurality of individual integrated circuitelements together form integrated circuits, in particular passivecircuits such as that of a filter or a mixer. In addition, integratedcircuit elements may realize at least a part of at least one activecircuit which is electrically connected to active individual componentson the surface of the substrate.

The bottom side of the substrate has external contacts for electricalconnection, for example to the circuit board of a terminal device.

Metallization layers are located primarily between the dielectricsubstrate layers. The top side and bottom side of the substrate, whichlikewise have metal structures, are also regarded as metallizationlayers here.

The top side of the substrate supports at least two conductor lines(metallizations), each of which constitutes in particular a contact forproducing electrical connection between the metallization layers in thesubstrate and the chip on the top of the substrate. Here the intervalbetween the named contacts according to the invention is smaller thanthat between the corresponding inter-layer connection in the topmostdielectric layer of the substrate, in order to enable connection of achip having an interval between the external electrodes which is lessthan the prescribed minimum interval between the inter-layer connectionsin the topmost layer of the substrate (e.g., 225 μm for ceramicsubstrates). Such “fanned-out” HF connections must be kept especiallyshort, in order to prevent influencing or damping of the signal when thecomponent is encapsulated, in particular in the extremely high frequencyrange.

The metallization layers in the interior of the substrate contain atleast two conductor lines, each of which connects in particular one ofthe inter-layer connections located in the underlying dielectric layerto one of the inter-layer connections located in an overlying dielectriclayer. Here the interval between the interface connections in the topdielectric layer according to the invention is chosen to be smaller thanthat in the underlying dielectric layer, in particular in order tomaintain the prescribed minimum interval in the latter layer (e.g., 350μm for ceramic substrates).

The contacting of the chip on a module substrate according to theinvention, or the contacting of the signal lines in variousmetallization layers in a (multi-layer) module substrate according tothe invention, is distinguished compared to the existing art by lowelectrical losses in the extremely high frequency range, in particularthe millimeter wave range. Compared to the usual contacting techniques,the contacting according to the present invention has the advantage thatit is especially space-saving and thereby enables an especially highdegree of integration in an extremely high frequency module. While knownextremely high frequency modules must forego encapsulation (with acasting compound) because of high losses, the contacting according tothe present invention enables encapsulation of the extremely highfrequency modules.

The invention will be explained in greater detail below on the basis ofexemplary embodiments and the corresponding schematic (and therefore nottrue-to-scale) figures.

FIG. 1 shows a schematic cross section of a component according to theinvention

FIG. 2 shows a perspective view of an HF connection according to theinvention, in a metallization layer in the interior of the substrate

FIG. 3 shows a perspective view of an HF connection according to theinvention on the surface of the substrate.

In FIG. 2, general features of the invention are explained on the basisof a perspective view of the metallization layers of a componentaccording to the invention.

FIG. 1 shows the schematic cross section of a component BE according tothe invention, having two chips CH1, CH2 positioned on a multilayersubstrate SU.

The HF connections in the component according to the invention arerealized by conductor lines LE (on the top of the substrate) or LS (inthe interior of the substrate). The conductor lines LS may also formintegrated circuit elements. The vertical signal feed-through in thesubstrate SU is accomplished by means of inter-layer connections DK1 andDK2.

If the smallest interval between two external electrodes is equal to orless than the minimum interval between the inter-layer connections DK1in the topmost layer of the substrate, then the inter-layer connectionsmay be positioned directly under the named external electrodes, asindicated for example for chip CH1. If the smallest interval betweenadjacent external electrodes is less than the minimum interval betweenthe inter-layer connections DK1 in the topmost layer of the substrate,it is necessary to fan out the conductor lines that realize HFconnections. The spreading of the HF connections on the top of thesubstrate preferably takes place beneath the chip area. General featuresof the HF connections according to the invention are explained in FIG.2.

The chips may include active and/or passive circuit elements (inparticular an inductance, a capacitor, a resistor, a diode or atransistor), or complete passive circuits (for example filters, mixers,a matching network). Moreover the possibility also exists of installingpassive discrete components, in particular coils, capacitors orresistors on the top of the substrate. It is possible for example, usingadditional discrete passive compensation structures, to compensate forthe detuning of the component caused by the housing.

The chips CH1, CH2 each have external electrodes AE, and areelectrically connected here by means of bumps BU to HF conductors LE orLS arranged on the substrate surface and hidden within the substrate SU.The bumps BU serve to produce an electrical connection between the HFconnections or conductor lines LS hidden in the substrate and the chipsCH1 and CH2, and possibly the other electronic components located on thetop of the substrate. For the extremely high frequency applications theheight of the bumps must be kept low enough so that only a smallquantity of the electromagnetic radiation emerging from the chip can beabsorbed by the protective layer. One possibility for achieving the lowheight of the flip-chip bumps is offered in particular bythermocompression bonding.

It is possible for the external electrodes AE of the chip to bepin-shaped (leads), or to be formed as SMD contacts.

The substrate SU has conductor lines LE to produce the named electricalcontact on the top and external contacts AK on the bottom to produce anelectrical connection with the circuit board of a terminal device. Theexternal contact AK may be designed as land grid arrays (LGAs), or maybe provided additionally with solder balls (μBGAs, or ball grid arrays).Also possible are pin-shaped external contacts (leads) and non-galvanictransitions between the component and the externally connectable circuitboard, for example waveguide transitions or slotted couplings.

In the preferred exemplary embodiment of the invention shown in FIG. 1,the chips CH1, CH2 are covered with a protective layer SF for protectionagainst humidity and external mechanical effects. The protective layeris preferably a dielectric layer or film. The chips are covered with thefilm by means of lamination. In the lamination process the film ispermanently deformed. The film covering is preferably made of a polymerthat exhibits especially low absorption of water, for example polyimide,fluorine-based polymers such as polytetrafluorethylene (PTFE) orpolyolefins such as (cross-linked) polypropylene or polyethylene. Thefilm covering may also be made of a metal and be filled with fibers orparticles. Moreover, the film covering may be or become coated withmetal or ceramic.

It is possible for the protective layer SF to completely and jointlycover the chips CH1, CH2 on the top of the component.

For mechanical stabilization, the chips in this exemplary embodiment arecovered with a casting compound GT. Optionally it is possible to leaveout the casting compound. Casting compound here means all substancesthat are applied in liquid state to the protective layer and becomesolid through curing (chemical reaction) or congealing (cooling). If thechip has no signal-conducting structures on its surface that needprotection (for example if all of the circuit elements and circuits arehidden in the multilayer substrate SU), it is possible to first coverthe chip with the casting compound, and only after the casting compoundhas cured to apply a protective layer or film covering.

The chips CH1, CH2 and the conductor lines LS may (individually ortogether) form at least part of the following circuits: a high-frequencyswitch, a matching circuit, an antenna, an antenna switch, a diodeswitch, a high-pass filter, a low-pass filter, a band-pass filter, aband-stop filter, a power amplifier, a diplexer, a duplexer, a coupler,a directional coupler, a storage element, a balun or a mixer.

The HF signal lines in the component according to the present inventionmay either be entirely hidden in the substrate, or at least part of thesignal line may be located on the top of the substrate.

FIG. 2 shows a schematic perspective top view of an HF line with thefanning according to the present invention in the interior of thesubstrate.

The interval between the inter-layer connections DK1 (for example amaximum of 340 μm) in the top dielectric layer of the substrate issmaller than the interval between the inter-layer connections DK2 in theunderlying layer of the substrate (for example at least 350 μm). Theconnection between the corresponding inter-layer connections is made ineach case by means of fanned-out conductor lines LS, which providecontact points for the inter-layer connectors to make contact. In thiscase the conductor lines LS1 of a metallizing level that is located in adeeper-lying layer of the substrate form a triplate line.

FIG. 3 shows the contacting technique according to the present inventionon the top of the substrate. With the help of the spread-out HFconnections formed by the conductor lines LE, the contact points KS forcontacting the chip may be made available at a smaller interval (forexample less than 220 μm) than the prescribed minimum interval betweenthe inter-layer connections DK1 in the top-most layer of the substrate(e.g., 225 μm). If a greater minimum interval is necessary between theinter-layer connections in the underlying layers of the substrate (e.g.,350 μm), the HF connections in the corresponding metallization layer maybe spread wider, for example from 225 μm to 350 μm.

Depending-on the number of conductor lines in the metallization layers,a component having contacting according to the present invention maycontain a microstrip line, or in some cases a “suspended microstrip”(the counterpart to a microstrip line, but which is not located on topof the substrate but in the interior of the substrate), a two-wire line,a three-wire line or triplate line, each of which runs for example in atleast two metallization layers. Here parts of the named lines areelectrically connected to each other by means of inter-layer connectionsthat are located above or below the corresponding metallization layers.

As indicated in FIG. 2, one HF line (for example the microstrip line,the two-wire line, the three-wire line or the triplate line) may run inat least two parallel metallization layers, with the vertical electricalconnection between the parts of the HF line that lie in the differentmetallization layers being accomplished by means of an inter-layerconnection.

In the interest of clarity, the invention has been presented on thebasis of only a few exemplary embodiments; but it is not restricted tothese. Additional possibilities are available in regard to the techniqueof connection between the individual component and the substrate andbetween the substrate and an external circuit board.

1-22. (canceled)
 23. A high frequency module comprising: a substratehaving multiple layers, the substrate comprising: metallization layerscomprising conductor lines; and dielectric layers comprising inter-layerconnections for connecting metallization layers; the metallizationlayers being located between the dielectric layers, on an upper surfaceof the substrate, and on a bottom surface of the substrate; and a firstinterval between inter-layer connections in a top-most dielectric layerbeing equal to or smaller than a second interval between inter-layerconnections in other dielectric layers; a chip on the substrate, thechip having external contacts to electrically connect the chip to themetallization layer on the upper surface of the substrate, a thirdinterval between the at least two external contacts of the chip beingsmaller than the first or second intervals; and a high frequencyconnection between the chip and the metallization layer on the bottomsurface of the substrate, the high frequency connection having at leasttwo conductor lines that are not electrically connected to each otherand being located in one or more metallization layers of the substrate.24. The module of claim 23, further comprising: a film for covering thechip.
 25. The module of claim 23, wherein the film comprises adielectric layer.
 26. The module of claim 23, further comprising: acasting compound for encapsulating the module.
 27. The module of claim23, wherein the high frequency connection is located on a surface of thesubstrate below the chip.
 28. The module of claim 23, wherein the highfrequency connection is between the dielectric layers.
 29. The module ofclaim 23, wherein the high frequency connection connects the externalcontacts of the chip with the metallization layer on the bottom surfaceof the substrate.
 30. The module of claim 23, further comprising firstand second chips on the substrate, the high frequency connectionconnecting at least one external contact of the first chip and at leastone external contact of the second chip with the metallization layer onthe bottom surface of the substrate.
 31. The module of claim 23, whereinthe high frequency connection connects a first metal structure in one ofthe metallization levels of the substrate with at least one externalcontact of a chip or with another metal structure.
 32. The module ofclaim 23, wherein the high frequency connection comprises a fanned-outhigh frequency connection.
 33. The module of claim 31, wherein thefanned-out high frequency connection is located in the metallizationlayer on the upper surface of the substrate below the chip.
 34. Themodule of claim 31, wherein the fanned-out high frequency connection islocated between the dielectric layers.
 35. The module of claim 23,wherein: the third interval is equal to or larger than the secondinterval; and the external contacts are directly above the inter-layerconnections located in the top-most dielectric layer.
 36. The module ofclaim 23, further comprising: a passive circuit element integrated intothe substrate, the passive circuit element being formed by a conductorline, an inter-layer connection, or both a conductor line and aninter-layer connection.
 37. The module of claim 35, wherein the passivecircuit element comprises a resonator, a directional coupler or afilter.
 38. The module of claim 23, wherein the inter-layer connectioncomprises an inductive element, a capacitive element, a connecting line,or a delay line.
 39. The module of claim 23, wherein the high frequencyconnection comprises a microstrip line, a two-wire line, or a three-wireline.
 40. The module of claim 23, wherein the high frequency connectionis between dielectric layers of the substrate and forms at least onepart of a triplate line.
 41. The module of claim 23, wherein at leastone inter-layer connection provides an electrical connection betweensegments of the high frequency connection that are located in differentmetallization layers.
 42. The module of claim 23, wherein: the thirdinterval between some of the external contacts is larger than the firstinterval; and at least one external contact is positioned directly abovean inter-layer connection located in the top-most dielectric layer. 43.The module of claim 23, wherein the chip comprises one or more of thefollowing: a diode and a transistor.
 44. The module of claim 23, whereinthe chip comprises a microwave chip, a millimeter wave chip, or anintegrated circuit component.
 45. The module of claim 23, wherein thechip is mechanically and electrically connected to the substrate via aflip-chip technique or a surface mounted device technique.
 46. Themodule of claim 23, wherein the substrate comprises at least twodielectric layers formed by low-temperature cofired ceramics orhigh-temperature cofired ceramics.